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W986416CH 1M x 16 bit x 4 Banks SDRAM
Features
* * * * * * * * * * * * * 3.3V0.3V power supply Up to 166 MHz clock frequency 1,048,576 words x 4 banks x 16 bits organization Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8 , and full page Burst read, Single Writes Mode Byte data controlled by UDQM and LDQM Power-Down Mode Auto-Precharge and controlled precharge 4k refresh cycles / 64ms Interface: LVTTL Package: TSOP II 54 pin, 400 mil - 0.80
General Description
W986416CH is a high speed synchronous dynamic random access memory (SDRAM), organized as 1M words x 4 banks x 16 bits. Using pipelined architecture and 0.20um process technology, W986416CH delivers a data bandwidth of up to 332M bytes per second (-6). For different application, W986416CH is sorted into four speed grades: -6, -7, -75 and -8H. The -6 parts can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3 specification. The -75 parts can run up to PC133/CL3 specification. The -8H parts can run up to 125Mhz/CL3 or PC100/CL2 specification. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986416CH is ideal for main memory in high performance applications.
Key Parameters
Symbol tCK tAC tRP tRCD ICC1 ICC4 ICC6 Description Clock Cycle Time Access Time from CLK Precharge to Active Command Active to Read/Write Command Operation Current ( Single bank ) Burst Operation Current Self-Refresh Current min/max min max min min max max max -6 6ns 5ns 18ns 18ns 80mA 130mA 1mA -7 7ns 5.4ns 20ns 20ns 65mA 115mA 1mA -75(PC133) 7.5ns 5.4ns 20ns 20ns 65mA 115mA 1mA -8H(PC100) 8ns 6ns 20ns 20ns 60mA 110mA 1mA
Revision 1.2 -1-
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
BLOCK DIAGRAM
CLK CLOCK BUFFER CKE
CS RAS CAS DECODER
CONTROL SIGNAL GENERATOR
COMMAND
COLUMN DECODER WE ROW DECODER ROW DECODER
COLUMN DECODER
A10
CELL ARRAY BANK #0
CELL ARRAY BANK #1
A0 ADDRESS BUFFER A9 A11 BS0 BS1
MODE REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
DMn
DATA CONTROL CIRCUIT
DQ BUFFER
DQ0 DQ15
REFRESH COUNTER
COLUMN COUNTER
UDQM LDQM
COLUMN DECODER ROW DECODER ROW DECODER
COLUMN DECODER
CELL ARRAY BANK #2
CELL ARRAY BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 4096 * 256 * 16.
Revision 1.2 -2-
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Pin Assignment
Pin Number 23 ~ 26, 22, 29 ~35 20, 21 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 19 Pin Name A0~ A11 BS0, BS1 DQ0 ~ DQ15 Function Address Bank Select Data Input/ Output Description Multiplexed pins for row and column address. Row address: A0 ~ A11. Column address: A0 ~ A7. Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input.
CS#
Chip Select
18 17 16 39, 15
RAS# CAS# WE# UDQM/ LDQM CLK CKE
Row Address Strobe Column Address Strobe Write Enable input/output mask Clock Inputs Clock Enable
Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock, RAS#, CAS# and WE# define the operation to be executed. Referred to RAS# Referred to RAS# The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from VCC, used for output buffers to improve noise. Separated ground from VSS, used for output buffers to improve noise. No connection
38 37
1, 14, 27 28, 41, 54 3, 9, 43, 49 6, 12, 46, 52 36, 40
VCC VSS VCCQ VSSQ NC
Power ( +3.3 V ) Ground Power ( + 3.3 V ) for I/O buffer Ground for I/O buffer No Connection
Revision 1.2 -3-
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Pin Assignment (Top View)
VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VCC Q DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
Revision 1.2 -4-
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
ABSOLUTE MAXIMUM RATINGS
SYMBOL VIN,VOUT VCC,VCCQ TOPR TSTG TSOLDER PD IOUT ITEM Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature(10s) Power Dissipation Short Circuit Output Current RATING -0.3~VCC+0.3 -0.3~4.6 0~70 -55~150 260 1 50 UNIT V V C C C W mA NOTES 1 1 1 1 1 1 1
RECOMMENDED DC OPERATING CONDITIONS ( Ta = 0 to 70C )
SYMBOL VCC VCCQ VIH VIL PARAMETER Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input High Voltage Input Low Voltage MIN 3.0 3.0 2.0 -0.3 TYP 3.3 3.3 MAX 3.6 3.6 VCC+0.3 0.8 UNIT V V V V NOTES 2 2 2 2
Note: VIH(max) = VCC/VCCQ+1.2V for pulse width < 5ns
VIL(min) = VSS/VSSQ-1.2V for pulse width < 5ns
CAPACITANCE (VCC=3.3V, Af = 1MHz, Ta=25C)
SYMBOL CI CO PARAMETER Input Capacitance (A0 to A11, BS0 ,BS1, CS, RAS, CAS, WE, DQM, CKE) Input Capacitance (CLK) Input/Output capacitance MIN MAX 4 4 6.5 UNIT pf pf pf
Note: These parameters are periodically sampled and not 100% tested.
Revision 1.2 -5-
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
AC CHARACTERISTICS AND OPERATING CONDITION (Vcc=3.3V0.3V, Ta=0 to 70C Notes:5, 6, 7, 8)
SYMBOL tRC tRAS tRCD tCCD tRP tRRD tWR tCK tCH tCL tAC tOH tHZ tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC PARAMETER Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b)Command Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time CL*=2 CL*=3 CLK Cycle Time CL*=2 CL*=3 CLK High Level width CLK Low Level width Access Time from CLK CL*=2 CL*=3 Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time -6 MIN 60 42 18 1 18 12 10 6 10 6 2.5 2.5 MAX 10000 MIN 63 42 20 1 20 14 10 7 10 7 2.5 2.5 -7 MAX 10000 -75(PC133) MIN MAX 65 45 10000 20 1 20 15 10 7.5 10 1000 7.5 1000 2.5 2.5 6 5.4 2.7 2.7 7.5 0 0 7.5 0.3 10 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 64 15 -8H(PC100) MIN MAX 68 48 10000 20 1 20 20 10 8 10 1000 8 1000 3 3 6 6 3 3 8 0 0 8 0.5 10 2 1 2 1 2 1 2 1 64 16 UNIT
Ns Cycle
1000 1000
1000 1000
6 5 2 2 0 0 0.3 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 12 6 6 10 2.5 2.5 0 0 0.3 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 14
6 5.4 7 7 10
ns
64
64
ms ns
* CL=CAS Latency
Revision 1.2 -6-
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
DC CHARACTERISTICS (VCC = 3.3V 0.3V, Ta=0~70C)
ITEMS OPERATING CURRENT tCK=min , tRC=min Active Precharge command cycling without Burst operation STANDBY CURRENT tCK=min , CS#=VIH VIH/L=VIH(min)/VIL(max) Bank : inactive state STANDBY CURRENT CLK=VIL , CS#=VIH VIH/L=VIH(min)/VIL(max) BANK : inactive state NO OPERATING CURRENT tCK=min CS#=VIH(min) BANK : active state (4 banks) BURST OPERATING CURRENT tCK = min Read / Write command cycling AUTO REFRESH CURRENT tCK = min Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh mode CKE = 0.2V SYMBOL -6 MAX. -7/-75(PC133) -8H(PC100) MAX. MAX. UNIT NOTES
1 bank operation
ICC1
80
65
60
3
CKE = VIH CKE = VIL (Power Down mode) CKE = VIH CKE = VIL (Power Down mode) CKE = VIH CKE= VIL (Power Down mode)
ICC2 ICC2P ICC2S ICC2PS ICC3 ICC3P ICC4
60 1 7 1 65 3 130
45 1 6 1 50 3 115
40 1 6 1 mA 45 3 110
3 3
3.4
ICC5
155
110
100
3
ICC6
1
1
1
ITEM INPUT LEAKAGE CURRENT ( 0V VIN VCC , all other pins not under test = 0V ) OUTPUT LEAKAGE CURRENT ( Output disable , 0V VOUT VCCQ ) LVTTL OUTPUT H LEVEL VOLTAGE ( IOUT = -2mA ) LVTTL OUTPUT L LEVEL VOLTAGE ( IOUT = 2mA )
SYMBOL II(L) IO(L) VOH VOL
MIN. -5 -5 2.4 -
MAX. 5 5 0.4
UNIT A A V V
NOTES
Revision 1.2 -7-
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
NOTES: 1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. The W986416CH-6/-7/-75/-8H is tested with 50pF output load. 5. Power up sequence is further described in the "Functional Description" section. 6. AC TESTING CONDITIONS
Output Reference Level Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signal Input Reference Level
1.4V/1.4V The W986416CH-6/-7/-75/-8H is tested with 50pF output load. (See diagram below) 2.4V/0.4V 2ns 1.4V
1.4 V
50 ohms
output
Z = 50 ohms 50pF
AC TEST LOAD
7 Transition times are measured between VIH and VIL. 8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
Revision 1.2 -8-
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table
command Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set No - Operation Burst Stop Device Deselect Auto - Refresh Self - Refresh Entry Self Refresh Exit Clock suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit Power Down Mode Exit Data write/Output Enable Data Write/Output Disable Device state Idle Any Any Active (3) Active (3) Active (3) Active (3) Idle Any Active (4) Any Idle Idle idle (S.R.) Active Idle Active (5) Active Any
(power down)
( note (1) , (2) )
BS0,1 A10 A11, A9-0 CS RAS CAS WE
CKEn-1
CKEn
DQM
Active Active
H H H H H H H H H H H H H L L H H H L L L H H
x x x x x x x x x x x H L H H L L L H H H x x
x x x x x x x x x x x x x x x x x x x x x L H
v v x v v v v v x x x x x x x x x x x x x x x
v L H L H L H v x x x x x x x x x x x x x x x
v x x v v v v v x x x x x x x x x x x x x x x
L L L L L L L L L L H L L H L x H L x H L x x
L L L H H H H L H H x L L x H x x H x x H x x
H H H L L L L L H H x L L x H x x H x x H x x
H L L L L H H L H L x H H x x x x x x x x x x
Notes: (1) v= valid x = Don't care L= Low Level H= High Level (2) CKEn signal is input level when commands are provided. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode.
Revision 1.2 -9-
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Functional Description
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC+0.3V on any of the input pins or VCC supplies. After power up, an initial pause of 200us is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS# activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max).
Read and Write Access Modes
After a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.
Revision 1.2 - 10 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode.
Burst Command
The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored.
Revision 1.2 - 11 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Table 2 Address Sequence of Sequential Mode
DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Access Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 BL= 8 (disturb addresses are A0, A1 and A2) No address carry from A2 to A3 Burst Length BL= 2 (disturb address is A0) No address carry from A0 to A1 BL= 4 (disturb addresses are A0 and A1) No address carry from A1 to A2
. Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.
. Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode
DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Access Address Burst Length BL = 2 BL = 4
A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 8
Revision 1.2 - 12 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Auto-Precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During autoprecharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency. A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with AutoPrecharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst write cycle. This delay is referred to as Write tDPL. The bank undergoing auto-precharge can not be reactivated until tDPL and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, A12, and A13, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP).
Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC cycle time plus the Self Refresh exit time. If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCES(min) + tCK(min).
Revision 1.2 - 13 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.
Revision 1.2 - 14 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Timing Waveform
Command Input Timing
tCL tCH
tCK
VIH CLK VIL
tT tCMS tCMH tCMH tT tCMS
CS
tCMS
tCMH
RAS
tCMS
tCMH
CAS
tCMS
tCMH
WE
tAS
tAH
A0-A11 BS0, 1
tCKS
tCKH
tCKS
tCKH
tCKS
tCKH
CKE
Revision 1.2 - 15 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A11 BS0, 1
tAC tLZ tOH
Valid Data-Out
tAC
tHZ tOH
Valid Data-Out
DQ
Read Command
Burst Length
Revision 1.2 - 16 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Control Timing of Input Data
(Word Mask)
CLK
tCMH tCMS tCMH tCMS
DQM
tDS tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ0 -15
(Clock Mask)
CLK
tCKH tCKS tCKH tCKS
CKE
tDS tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ0 -15
Control Timing of Output Data
(Output Enable)
CLK
tCMH tCMS tCMH tCMS
DQM
tAC tOH tOH
Valid Data-Out
tAC tOH
Valid Data-Out
tHZ tLZ
tAC tOH
Valid Data-Out
tAC
DQ0 -15
OPEN
(Clock Mask)
CLK
tCKH tCKS tCKH tCKS
CKE
tAC tOH tAC tOH
Valid Data-Out Valid Data-Out
tAC tOH tOH
Valid Data-Out
tAC
DQ0 -15
Revision 1.2 - 17 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Mode Register Set Cycle
tRSC
CLK
tCMS tCMH
CS
tCMS
tCMH
RAS
tCMS tCMH
CAS
tCMS tCMH
WE
tAS tAH
Register set data
A0-A10 BS
A0 A1 A2 A3 A4 A5 A6 A7 A0 A8 A9 A0 A10 A0 A11 BS0 BS1 A0 "0" "0" "0" "0" A0 Reserved "0" "0" (Test Mode) Reserved Write Mode A0 CAS Latency Addressing Mode Burst Length
A2 0 0 0 0 1 1 1 1
A0 A0 A1 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A3 A0 A0 0 A0 1
A0 0 1 0 1 0 1 0 1
next command BurstA0 Length Sequential A0 Interleave A0 1 A0 1 A0 2 A0 2 A0 A0 4 4 A0 A0 8 8 Reserved A0 FullA0 Page Addressing Mode A0 A0 Sequential Interleave A0 A0 Reserved
A6 0 0 0 0 1
A0 A5 A0 0 A0 0 A0 1 A0 1 A0 0 A0 A9 A0 0 A0 1
A4 0 1 0 1 0
CAS A0 Latency Reserved A0 Reserved A0 2 A0 3 Reserved Single Write Mode Burst read and Burst write A0 Burst read and single write A0
Revision 1.2 - 18 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Operating Timing Example
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRC tRC tRC tRC tRAS tRP tRP tRAS
RAS
tRAS tRP tRAS
CAS
WE BS0 BS1
tRCD tRCD
RBb RAc
tRCD
RBd
tRCD
RAe
A10 A0-A9, A11 DQM
RAa
RAa
CAw
RBb
CBx
RAc
CAy
RBd
CBz
RAe
CKE
tAC tAC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
tAC
cy0 cy1 cy2 cy3
tAC
DQ
tRRD
tRRD
tRRD
tRRD
Bank #0 Active Bank #1 Bank #2 Idle Bank #3
Read Active
Precharge Read
Active
Read Precharge Active
Precharge Read
Active
Revision 1.2 - 19 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRC tRC tRC tRC tRAS tRP tRP tRAS
RAS
tRAS tRP tRAS
CAS
WE BS0 BS1
tRCD tRCD
RBb RAc
tRCD
tRCD
RBd RAe
A10
RAa
A0-A9, A11 DQM CKE
RAa
CAw
RBb
CBx
RAc
CAy
RBd
CBz
RAe
tAC
tAC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
tAC
cy0 cy1 cy2 cy3
tAC
dz0
DQ
tRRD
tRRD
tRRD
tRRD
Bank #0 Bank #1 Bank #2 Idle Bank #3
Active
Read Active
AP* Read
Active
Read AP* Active
AP* Read
Active
* AP is the internal precharge start timing
Revision 1.2 - 20 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length=8, CAS Latency=3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRC tRC tRC
RAS
tRAS tRP tRP tRAS tRAS tRP
CAS
WE BS0 BS1
tRCD tRCD
RBb RAc
tRCD
A10
RAa
A0-A9 A11 DQM
RAa
CAx
RBb
CBy
RAc
CAz
CKE
tAC tAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6
tAC
by7 CZ0
DQ
tRRD
tRRD
Bank #0 Bank #1 Bank #2
Active
Read Precharge Active Read
Precharge
Active
Read Precharge
Idle Bank #3
Revision 1.2 - 21 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length=8, CAS Latency=3, Autoprecharge)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8
tRC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK CS
tRC
RAS
tRAS tRP tRAS tRAS tRP
CAS
WE BS0 BS1
tRCD tRCD tRCD
RBb RAc
A10
RAa
A0-A9
RAa
CAx
RBb
CBy
RAc
CAz
DQM
CKE
tCAC
tCAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5
tCAC
by6 CZ0
DQ
tRRD
tRRD
Bank #0 Bank #1 Bank #2
Active
Read Active
AP* Read
Active
Read AP*
Idle Bank #3 * AP is the internal precharge start timing
Revision 1.2 - 22 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Write (Burst Length=8)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRC
RAS
tRAS tRP tRAS tRAS tRP
CAS
tRCD tRCD tRCD
WE
BS0 BS1
A10
RAa
RBb
RAc
A0-A9, A11 DQM
RAa
CAx
RBb
CBy
RAc
CAz
CKE DQ
ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2
tRRD
tRRD
Bank #0 Bank #1 Bank #2 Bank #3
Active
Write Active Write
Precharge
Active
Write Precharge
Idle
Revision 1.2 - 23 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Write (Burst Length=8, Autoprecharge)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRC
RAS
tRAS tRP tRAS tRAS tRP
CAS
WE
BS0
BS1
tRCD tRCD
RBb RAb
tRCD
A10
RAa
A0-A9, A11 DQM CKE DQ
RAa
CAx
RBb
CBy
RAc
CAz
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
tRRD
Bank #0 Active Bank #1 Bank #2 Idle Bank #3
Write Active
AP* Write
Active
Write AP*
* AP is the internal precharge start timing
Revision 1.2 - 24 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Page Mode Read (Burst Length=4, CAS Latency=3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
tCCD tCCD tCCD
CS
tRAS tRAS tRP tRP
RAS
CAS
WE
BS0
BS1
tRCD tRCD
RBb
A10 A0-A9, A11 DQM CKE
RAa
RAa
CAI
RBb
CBx
CAy
CAm
CBz
tAC
tAC
a0 a1 a2 a3 bx0 bx1
tAC
tAC
am1
tAC
am0 am2 bz0 bz1 bz2 bz3
DQ
tRRD
Ay0
Ay1
Ay2
Bank #0 Active Bank #1 Bank #2 Idle Bank #3
Read Active Read
Read
Read Read
Precharge AP*
* AP is the internal precharge start timing
Revision 1.2 - 25 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Page Mode Read / Write (Burst Length=8, CAS Latency=3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRAS tRP
RAS CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9, A11
RAa
CAx
CAy
DQM CKE
tAC tWR
ax0 ax1 ax2 ax3 ax4 ax5 ay0 ay1 ay2 ay3 ay4
DQ
QQ
Q
Q
Q
Q
D
D
D
D
D
Bank #0 Bank #1 Bank #2 Bank #3
Active
Read
Write
Precharge
Idle
Revision 1.2 - 26 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
AutoPrecharge Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRC tRC
RAS
tRAS tRP tRAS tRP
CAS
WE BS0
BS1
tRCD tRCD
RAb
A10
RAa
A0-A9, A11 DQM CKE
RAa
CAw
RAb
CAx
tAC
tAC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
DQ
Bank #0 Bank #1 Bank #2
Active
Read
AP*
Active
Read
AP*
Idle Bank #3 * AP is the internal precharge start timing
Revision 1.2 - 27 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
AutoPrecharge Write (Burst Length = 4)
(CLK = 100 MHz) CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
tRC tRC
RAS
tRAS tRP tRAS tRP
CAS
WE BS0
BS1
tRCD
RAb RAc
3CK
A10 A0-A9, A11 DQM CKE DQ
RAa
RAa
CAw
RAb
CAx
RAc
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
Bank #0 Bank #1 Bank #2
Active
Write
AP*
Active
Write
AP*
Active
Idle Bank #3 * AP is the internal precharge start timing
Revision 1.2 - 28 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
AutoRefresh cycle
0 1 2 3 4 5 6 7 8 9
(CLK = 100 MHz)
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
tRP tRC tRC
CS
RAS
CAS
WE
BS0,1
A10
A0-A9, A11
DQM
CKE DQ
All Banks Prechage
Auto Refresh
Auto Refresh (Arbitrary Cycle)
Revision 1.2 - 29 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
SelfRefresh Cycle
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRP
RAS CAS
WE
BS0,1
A10
A0-A9, A11
DQM
tSB
tCKS
tCKS
CKE
tCKS
DQ
tRC
Self Refresh Cycle
No Operation Cycle
All Banks Precharge
Self Refresh Entry
Arbitrary Cycle
Revision 1.2 - 30 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Burst Read and Single Write (Burst Lenght = 4, CAS Latency = 3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS RAS
CAS
tRCD
WE BS0
BS1
A10
RBa
A0-A9, A11 DQM CKE
RBa
CBv
CBw
CBx
CBy
CBz
tAC
tAC
av0 Q av1 Q av2 Q av3 Q aw0 D ax0 D ay0 D az0 Q az1 Q az2 Q az3 Q
DQ
Bank #0 Active Bank #1 Bank #2 Bank #3 Idle
Read
Single Write Read
Revision 1.2 - 31 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
PowerDown Mode
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
WE
BS
A10
RAa
RAa
A0-A9
RAa
CAa
RAa
CAx
DQM
tSB tSB
CKE
tCKS tCKS
ax0 ax1 ax2
tCKS
ax3
tCKS
DQ
Active
NOP Wrate Active Standby Power Down mode
Precharge
NOPActive Precharge Standby Power Down mode
Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode. When CKE goes high, command input must be No operation at next CLK rising edge.
Revision 1.2 - 32 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Autoprecharge Timing ( Read Cycle )
0
(1) CAS Latency=2
( a ) burst length = 1 Command DQ ( b ) burst length = 2 Command DQ ( c ) burst length = 4 Command DQ ( d ) burst length = 8 Command DQ
1 AP
2
3 Act
4
5
6
7
8
9
10
11
Read
tRP
Q0 Read AP
tRP
Act Q1 AP
tRP
Q0 Read Q0 Read Q0 Read AP
tRP
Act Q3 AP
tRP
Q1 Q1
Q2 Q2 Act
Act
Q3
Q4
Q5
Q6
Q7
(2) CAS Latency=3
( a ) burst length = 1 Command DQ ( b ) burst length = 2 Command DQ ( c ) burst length = 4 Command DQ ( d ) burst length = 8 Command
Q0 Read AP
tRP
Act Q0 Q1 AP
tRP
Read Q0 Read Q0
Act Q2 Q3 AP
tRP
Q1
Act Q6 Q7
DQ
Q1
Q2
Q3
Q4
Q5
Note ) Read AP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least t RAS(min).
Revision 1.2 - 33 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Autoprecharge timing ( Write Cycle )
0
(1) CAS Latency=2
( a ) burst length = 1 Command
1
2
3
4
5
6
7
8
9
10
11
Write
tWR
AP
tRP
Act
DQ ( b ) burst length = 2 Command
D0 Write
tWR
AP
tRP
Act
DQ ( c ) burst length = 4 Command
D0 Write
D1 AP
tWR tRP
Act
DQ ( d ) burst length = 8 Command
D0 Write
D1
D2
D3 AP
tWR tRP
Act
DQ
(2) CAS Latency=3
( a ) burst length = 1 Command DQ ( b ) burst length = 2 Command
D0 Write
tWR
D1 AP
D2
tRP
D3
D4 Act
D5
D6
D7
D0 Write
tWR
AP
tRP
Act
DQ ( c ) burst length = 4 Command
D0 Write
D1 AP
tWR tRP
Act
DQ ( d ) burst length = 8 Command
D0 Write
D1
D2
D3 AP
tWR tRP
Act
DQ
D0
D1
D2
D3
D4
D5
D6
D7
Note ) Write AP Act
represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS(min) .
Revision 1.2 - 34 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Timing Chart of Read to Write cycle In the case of Burst Length=4
0
(1) CAS Latency=2
( a ) Command DQM DQ
1
2
3
4
5
6
7
8
9
10
11
Read Write
D0 Read
D1 Write D0
D2
D3
( b ) Command DQM
DQ
D1
D2
D3
(2) CAS Latency=3
( a ) Command DQM DQ
Read Write D0 Read D1 Write D0 D1 D2 D3 D2 D3
( b ) Command DQM DQ
Note )
The Output data must be masked by DQM to avoid I/O conflict
Revision 1.2 - 35 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Timing Chart of Write-to-Read cycle
In the case of Burst Length=4
0
(1) CAS Latency=2
( a ) Command DQM DQ ( b ) Command DQM DQ
1
2
3
4
5
6
7
8
9
10
11
Write Read D0 Write D0 D1 Read Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
(2) CAS Latency=3
( a ) Command DQM DQ ( b ) Command DQM
Write Read D0 Write D0 D1 Read Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
DQ
Revision 1.2 - 36 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Timing chart of Burst Stop cycle ( Burst stop Command )
0
(3) Read cycle
( a ) CAS latency =2
Command
1
2
3
4
5 BST
6
7
8
9
10
11
Read Q0 Read Q0 Write D0 D1 D2 D3 D4 Q1 Q1 Q2
DQ
Q3 BST Q2 BST
Q4
( b )CAS latency = 3
Command
DQ
Q3
Q4
(2) Write cycle
Command
DQ
Note )
BST
represents the Burst stop command
Revision 1.2 - 37 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Timing chart of Burst Stop cycle ( Precharge Command )
In the case of Burst Lenght = 8
0
(1) Read cycle ( a )CAS latency =2
Commad
1
2
3
4
5
6
7
8
9
10
11
Read Q0 Read Q0 Q1 Q1 Q2
PRCG
DQ
Q3
PRCG
Q4
( b )CAS latency = 3
Commad
DQ
Q2
Q3
Q4
(2) Write cycle ( a ) CAS latency =2
Commad DQM DQ
Write D0 Write D4 D1 D2 D3 D4
PRCG
tWR
( b )CAS latency = 3
Commad
PRCG
tWR
DQM DQ
D0
Note )
D1
PRCG
D2
D3
represents the Precharge command
Revision 1.2 - 38 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
CKE/DQM Input timing ( Write cycle )
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
D1
D2
D3
DQM MASK (1)
D5
CKE MASK
D6
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
D1
D2
D3
DQM MASK (2)
D5
CKE MASK
D6
CLK cycle No. External CLK Internal CKE DQM DQ
1
2
3
4
5
6
7
D1
D2
D3
CKE MASK (3)
D4
D5
D6
Revision 1.2 - 39 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
CKE/DQM Input timing ( Read cycle )
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM
DQ
Q1
Q2
Q3
Q4
Open Open (1)
Q6
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
Q1
Q2
Q3
Q4
Open
Q6
(2)
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
Q1
Q2
Q3
Q4
Q5
Q6
(3)
Revision 1.2 - 40 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Self Refresh/Power Down Mode Exit Timing Asynchronous Control Input Buffer turn on time ( Power down mode exit time ) is specified by t CKS(min) + tCK(min) A ) tCK < tCKS(min)+tCK(min)
tCK
CLK CKE
tCKS(min)+tCK(min)
Command
NOP
Command
Input Buffer Enable
B) tCK >= tCKS(min) + tCK (min)
tCK CLK
CKE
tCKS(min)+tCK(min)
Command
Command
Input Buffer Enable
Note ) All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode
NOP Command
Represents the No-Operation command Represents one command
Revision 1.2 - 41 -
Publication Release Date: June, 1999
W986416CH 1M x 16 bit x 4 Banks SDRAM
Package Dimension
54L TSOP (II)-400 mil
54 28
E
HE
1 e
27
b C
D
L A2 ZD A1 A L1
Y
SEATING PLANE
Controlling Dimension : Millimeters
DIMENSION (MM)
SYMBOL
DIMENSION (INCH) MAX.
1.20
MIN. A
A1 A2 b c D E HE e L L1 Y ZD 0.40 22.12 10.06 11.56 0.24 0.05
NOM.
MIN.
NOM.
MAX.
0.047
0.10 1.00 0.32 0.15 22.22 10.16 11.76 0.80 0.50 0.80
0.15
0.002
0.004 0.039
0.006
0.40
0.009
0.012 0.006 0.875 0.400 0.463 0.0315
0.016
22.62 10.26 11.96
0.871 0.396 0.455
0.905 0.404 0.471
0.60
0.016
0.020 0.032
0.024
0.10 0.71 0.028
0.004
Revision 1.2 - 42 -
Publication Release Date: June, 1999

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